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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
ORDERING GUIDE SUMMARY Model LSN2-T/6-W3 LSN2-T/6-D12 LSN2-T/10-W3 LSN2-T/10-D12 LSN2-T/16-W3 LSN2-T/16-D12 VOUT Range 0.75-3.3V 0.75-5V 0.75-3.3V 0.75-5V 0.75-3.3V 0.75-5V IOUT Range 0-6A 0-6A 0-10A 0-10A 0-16A 0-16A VIN Range 2.4-5.5V 8.3-14V 2.4-5.5V 8.3-14V 2.4-5.5V 8.3-14V Ripple/Noise 15mVp-p 15mVp-p 15mVp-p 30mVp-p 25mVp-p 30mVp-p Efficiency 94% 95% 95% 95% 95% 94%
INPUT CHARACTERISTICS Parameter
Voltage Range
Typ. @ 25C, full load
2.4-5.5 or 8.3-14V 4.22 to 11.12A Included 60mA Positive or negative polarity
Notes
5V or 12V nominal models Model dependent With autorestart hysteresis Output is short circuited Default polarity is positive
FEATURES
Current, full power Undervoltage Shutdown Short Circuit Current Remote On/Off Control OUTPUT CHARACTERISTICS Parameter Voltage Current Power Dissipation Accuracy Ripple & Noise Line and Load Regulation Overcurrent Protection Overtemperature Protection Efficiency (minimum) Efficiency (typical) GENERAL SPECIFICATIONS Parameter Transient Response Operating Temperature Range Safety EMI MECHANICAL CHARACTERISTICS 6 Amp output models 10 & 16 Amp models
User-selectable outputs: 0.75-5V (D12 models) or 0.75-3.3V (W3 models) 6, 10 or 16A maximum output current Double lead free to RoHS standards Selectable phased start-up sequencing and tracking Wide range VIN 8.3-14V or 2.4-5.5V Up to 52 Watts total output power Very high efficiency up to 95% Starts up into pre-biased load Fast settling, high di/dt IOUT slew rate

Typ. @ 25C, full load 0.75-3.3 or 0.75-5V 0-6, 0-10 or 0-16A 20, 33, 52W max. 2% of VNOM 15-75mVpp 0.03% Hiccup autorecovery +115C shutdown 92-93% 94-95%
Notes User adjustable, model dependent Three ranges, model dependent Three values, model dependent 50% load Model dependent Continuous short circuit protection Model dependent Model dependent

DESCRIPTION
These miniature point-of-load (POL) switching DC/DC converters are ideal regulation and supply elements for distributed power and intermediate bus architectures. Fully compatible with the Distributed-power Open Standards Alliance specification (www.dosapower.com), LSN2's can power CPU's, programmable logic and mixedvoltage systems with little heat and low noise. A typical application uses a master isolated 12 or 5Vdc supply and individual LSN2 converters for local 1.8 and 3.3Vdc supplies. All system isolation resides in the central supply, leaving lower cost POL regulation at the load. The LSN2's can deliver very high power (to 52 Watts) in a tiny area without heat sinking or external components. They feature quick transient response (to 25sec) and very fast current slew rates (to 20A/sec).
Typ. @ 25C, full load 25sec -40 to +85C UL/IEC/EN 60950 FCC pt.15, class B
Notes 50% load step to 2% of final value With 200 lfm airflow And CSA C22.2-No.234
0.50 x 1.00 x 0.275 inches (12.7 x 25.4 x 6.98 mm) 0.50 x 2.00 x 0.32 inches (12.7 x 50.8 x 8.13 mm)
Pb
Lead-free construction/attach
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LSN2 Series Page 1 of 14
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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
PERFORMANCE SPECIFICATIONS AND ORDERING GUIDE Output Model
LSN2-T/6-W3 LSN2-T/6-D12 LSN2-T/10-W3 LSN2-T/10-D12 LSN2-T/16-W3 LSN2-T/16-D12
Input Regulation Line
0.3% 0.3% 0.3% 0.3% 0.3% 0.3%
VOUT (Volts)
0.75-3.3 0.75-5 0.75-3.3 0.75-5 0.75-3.3 0.75-5
IOUT (Amps)
6 6 10 10 16 16
Power (Watts)
19.8 19.8 33.0 33.0 52.8 52.8
R/N (mVp-p) Typ.
15 15 15 30 25 30
Max.
25 25 25 75 50 75
Load
0.3% 0.3% 0.3% 0.3% 0.3% 0.3%
VIN Nom. (Volts)
5 12 5 12 5 12
Range (Volts)
2.4-5.5 8.3-14 2.4-5.5 8.3-14 2.4-5.5 8.3-14
IIN (mA/A)
50/4.22 70/2.69 50/6.95 100/4.39 50/11.12 100/7.1
Efficiency Min.
92% 90% 93% 93% 93% 92%
Typ.
94% 93% 95% 95% 95% 94%
Package (Case/ Pinout)
B12, P69 B12, P69 B11, P68 B11, P68 B11, P68 B11, P68
Typical at TA = +25C under nominal line voltage and full-load conditions, unless noted. All models are tested and specified with external 22F tantalum input and output capacitors. These capacitors are necessary to accommodate our test equipment and may not be required to achieve specified performance in your applications. See I/O Filtering and Noise Reduction. Ripple/Noise (R/N) is tested/specified over a 20MHz bandwidth and may be reduced with external filtering. See I/O Filtering and Noise Reduction for details.
These devices have no minimum-load requirements and will regulate under no-load conditions. Regulation specifications describe the output-voltage deviation as the line voltage or load is varied from its nominal/midpoint value to either extreme. Nominal line voltage, no-load/full-load conditions. VIN must be 0.5V greater than VOUT. LSN2-TXX-D12 efficiencies are shown at 5VOUT.
PART NUMBER STRUCTURE
L SN2 - T / 16 - D12 N G - C
Output Configuration: L = Unipolar Low Voltage Non-Isolated SMT Nominal Output Voltage: 0.75-3.3 Volts (W3) 0.75-5 Volts (D12) Maximum Rated Output Current in Amps RoHS-6 compliant* Power Good Output: Blank = Omitted G = Installed On/Off Polarity: Blank = Positive polarity N = Negative polarity Input Voltage Range: D12 = 8.3-14 Volts (12V nominal) W3 = 2.4-5.5 Volts (5V nominal) Note: Not all model number combinations are available. Contact C&D Technologies (DATEL). *Contact C&D Technologies (DATEL) for availability.
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LSN2 Series Page 2 of 14
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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
Short Circuit Duration Prebias Startup (16) Sequencing Slew Rate Startup delay until sequence start Tracking accuracy, rising input Tracking accuracy, falling input Sequence pin input impedance Remote Sense to VOUT Power Good Output ("G" suffix) Power_Good Configuration
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Performance/Functional Specifications (1)
INPUT
Input Voltage Range Isolation Start-Up Threshold W3 Models 12V Models Undervoltage Shutdown W3 Models 12V Models Overvoltage Shutdown Reflected (Back) Ripple Current (2) Internal Input Filter Type Reverse Polarity Protection Input Current: Full Load Conditions Inrush Transient Shutdown Mode (Off, UV, OT) Output Short Circuit No Load W3 models 12V models Low Line (VIN = VMIN) LSN2-T/6-W3 LSN2-T/6-D12 LSN2-T/10-W3 LSN2-T/10-D12 LSN2-T/16-W3 LSN2-T/16-D12 Remote On/Off Control: Positive Logic (no model suffix) Negative Logic ("N" model suffix) Current
(5)
Continuous, no damage (output shorted to ground) Converter will start up if the external output voltage is less than VNOM 2V max. per millisecond 10 milliseconds VOUT = 100mV of Sequence In VOUT = 200mV of Sequence In 400k to 1M 0.5V max. (7) TRUE (OK) = open drain FALSE (not OK) = Signal Ground to 0.4V MOSFET to ground with external user pullup, 10mA max. sink
See Ordering Guide Not isolated, input and output commons are internally connected 2.2 Volts 8 Volts 2.0 Volts 7.5 Volts None 10-70mAp-p (model dependent) Capacitive See fuse information See Ordering Guide 0.1A2sec 5mA 60mA 50mA 100mA 5.54 Amps 3.85 Amps 9.14 Amps 6.31 Amps 14.63 Amps 10.2 Amps OFF = ground pin to +0.8V max. ON = open pin or +2.5V min. to +VIN max. ON = open pin to +0.3V max. OFF = +2.5V min. to +VIN max. 1mA max. See Ordering Guide No minimum load 2% of VNOM See Ordering Guide 0.02% of VOUT range per C See Ordering Guide and (8) See Ordering Guide and (10) See Ordering Guide
DYNAMIC CHARACTERISTICS
Dynamic Load Response 25sec to 2% of final value (50-100-50% load step, di/dt = 20A/msec) Start-Up Time 4-7msec for VOUT = nominal (VIN on to VOUT regulated or On/Off to VOUT) Switching Frequency LSN2-T/6 models LSN2-T/10 and -T/16 models 315kHz 230kHz TBC Hours
ENVIRONMENTAL
Calculated MTBF (4) Operating Temperature Range (Ambient) No derating, natural convection -40 to +63C, vertical mount, 2.5VOUT (9) With derating See Derating Curves Operating PC Board Temperature Storage Temperature Range Thermal Protection/Shutdown Density Altitude Relative Humidity -40 to +100C max. (12) -55 to +125C +115C 0 to 10,000 feet 10% to 90%, non-condensing See Mechanical Specifications Nylon 46 0.28 ounces (7.8 grams) FCC part 15, class B, EN55022 (may need external filter) UL/cUL 60950 CSA-C22.2 No.234 IEC/EN 60950 UL94V-0
PHYSICAL
Outline Dimensions Removable Heat Shield Weight Electromagnetic Interference (conducted and radiated) Safety Flammability Rating
OUTPUT
Voltage Output Range Minimum Loading Accuracy (50% load) Voltage Adjustment Range (13) Temperature Coefficient Ripple/Noise (20 MHz bandwidth) Line/Load Regulation (See Tech Notes) Efficiency Maximum Capacitive Loading: (15) LSN2-T/6 models: Cap-ESR = 0.001 to 0.01 Cap-ESR >0.01 LSN2-T/10 and -T/16 models: Cap-ESR = 0.001 to 0.01 Cap-ESR >0.01 Current Limit Inception: (98% of VOUT) LSN2-T/6 models LSN2-T/10 models LSN2-T/16 models Short Circuit Mode (6) Short Circuit Current Output Protection Method (17)
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Continuous or transient) W3 models 12V models On/Off Control Input Reverse Polarity Protection Output Current (7) +7 Volts +15 Volts -0.3V min. to +VIN max. See Fuse section Current-limited. Devices can withstand sustained short circuit without damage. Storage Temperature -55 to +125C Lead Temperature (soldering 10 sec. max.) +280C
These are stress ratings. Exposure of devices to any of these conditions may adversely affect long-term reliability. Proper operation under conditions other than those listed in the Performance/Functional Specifications Table is not implied.
3000F 5000F 5000F 10,000F 11-13 Amps (cold startup) 11 Amps (after warm up) 18.75 Amps (cold startup) 16.75 Amps (after warm up) 24 Amps (cold startup) 21 Amps (after warm up) 600mA Hiccup autorecovery on overload removal
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LSN2 Series Page 3 of 14
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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
Output noise may be further reduced by adding an external filter. See I/O Filtering and Noise Reduction. (9) All models are fully operational and meet published specifications, including "cold start" at -40C. VOUT is nominal. (10) Regulation specifications describe the deviation as the line input voltage or output load current is varied from a nominal midpoint value to either extreme. (11) Other input or output voltage ranges are available under scheduled quantity special order. (12) Maximum PC board temperature is measured with the sensor in the center. (13) Do not exceed maximum power specifications when adjusting the output trim. (14) When Sequencing is not used, the Power Good output is TRUE at any time the output is within approximately 10% of the voltage set point. Power Good basically indicates if the converter is in regulation. Power Good detects Over Temperature if the PWM has shut down due to OT. Power Good does not directly detect Over Current. If Sequencing is in progress, Power Good will falsely indicate TRUE (valid) before the output reaches its setpoint. Ignore Power Good if Sequencing is in transition. (15) The maximum output capacitive loads depend on the the Equivalent Series Resistance (ESR) of the external output capacitor. (16) Do not use Pre-bias startup and sequencing together. See Technical Notes below. (17) After short circuit shutdown, if the load is partially removed such that the load still exceeds the overcurrent (OC) detection, the converter will remain in hiccup restart mode. (18) For best noise performance, leave the Track/Sequence pin OPEN when not used.
(8)
Performance/Functional Specification Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
All models are tested and specified with external 1 || 10F ceramic/tantalum output capacitors and a 22F external input capacitor. All capacitors are low ESR types. These capacitors are necessary to accommodate our test equipment and may not be required to achieve specified performance in your applications. All models are stable and regulate within spec under no-load conditions. General conditions for Specifications are +25C, VIN = nominal, VOUT = nominal, full load. "Nominal" output voltage is +5V for D12 models and +3.3V for W3 models. Input Back Ripple Current is tested and specified over a 5-20MHz bandwidth. Input filtering is CIN = 2 x 100F tantalum, CBUS = 1000F electrolytic, LBUS = 1H. Note that Maximum Power Derating curves indicate an average current at nominal input voltage. At higher temperatures and/or lower airflow, the DC/DC converter will tolerate brief full current outputs if the total RMS current over time does not exceed the derating curve. Mean Time Before Failure is calculated using the Telcordia (Belcore) SR-332 Method 1, Case 3, ground fixed conditions, TPCBOARD = +25C, full output load, natural air convection. The On/Off Control may be driven with external logic or by applying appropriate external voltages which are referenced to -Input Common. The On/Off Control Input should use either an open collector/open drain transistor or logic gate which does not exceed +VIN. A 68K external pullup resistor to +VIN will cause the "ON" state for negative logic models. Short circuit shutdown begins when the output voltage under increasing load degrades approximately 2% from the selected setting. If Sense is connected remotely at the load, up to 0.5 Volts difference is allowed between the Sense and +VOUT pins to compensate for ohmic voltage drop in the power lines. A larger voltage drop may cause the converter to exceed maximum power dissipation.
Figure 1. LSN2 Series Simplified Schematic
TECHNICAL NOTES
output capacitors are specified for low ESR and full-range frequency response. In critical applications, input/output ripple/noise may be further reduced using filtering techniques, the simplest being the installation of external I/O caps. External input capacitors serve primarily as energy-storage devices. They minimize high-frequency variations in input voltage (usually caused by IR drops in conductors leading to the DC/DC) as the switching converter draws pulses of current. Input capacitors should be selected for bulk capacitance (at appropriate frequencies), low ESR, and high rms-ripple-current ratings. The switching nature of modern DC/DC's requires that the dc input voltage source have low ac impedance at the frequencies of interest. Highly inductive source impedances can greatly affect system stability. Your specific system configuration may necessitate additional considerations.
I/O Filtering and Noise Reduction All models in the LSN2 Series are tested and specified with external 1 || 10F ceramic/tantalum output capacitors and a 22F tantalum input capacitor. These capacitors are necessary to accommodate our test equipment and may not be required to achieve desired performance in your application. The LSN2's are designed with high-quality, high-performance internal I/O caps, and will operate within spec in most applications with no additional external components. In particular, the LSN2's input capacitors are specified for low ESR and are fully rated to handle the units' input ripple currents. Similarly, the internal
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LSN2 Series Page 4 of 14
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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
installed within the ungrounded input path to the converter. Safety Considerations LSN2 SIPs are non-isolated DC/DC converters. In general, all DC/DC's must be installed, including considerations for I/O voltages and spacing/separation requirements, in compliance with relevant safety-agency specifications (usually UL/IEC/EN60950). In particular, for a non-isolated converter's output voltage to meet SELV (safety extra low voltage) requirements, its input must be SELV compliant. If the output needs to be ELV (extra low voltage), the input must be ELV. Input Overvoltage and Reverse-Polarity Protection
Figure 2. Measuring Input Ripple Current
Output ripple/noise (also referred to as periodic and random deviations or PARD) may be reduced below specified limits with the installation of additional external output capacitors. Output capacitors function as true filter elements and should be selected for bulk capacitance, low ESR, and appropriate frequency response. Any scope measurements of PARD should be made directly at the DC/DC output pins with scope probe ground less than 0.5" in length.
LSN2 SIP Series DC/DC's do not incorporate either input overvoltage or input reverse-polarity protection. Input voltages in excess of the specified absolute maximum ratings and input polarity reversals of longer than "instantaneous" duration can cause permanent damage to these devices. Start-Up Time The VIN to VOUT Start-Up Time is the interval between the time at which a ramping input voltage crosses the lower limit of the specified input voltage range and the fully loaded output voltage enters and remains within its specified accuracy band. Actual measured times will vary with input source impedance, external input capacitance, and the slew rate and final value of the input voltage as it appears to the converter. The On/Off to VOUT Start-Up Time assumes the converter is turned off via the On/Off Control with the nominal input voltage already applied to the converter. The specification defines the interval between the time at which the converter is turned on and the fully loaded output voltage enters and remains within its specified accuracy band. See Typical Performance Curves. Remote Sense LSN2 Series offer an output sense function. The sense function enables pointof-use regulation for overcoming moderate IR drops in conductors and/or cabling. Since these are non-isolated devices whose inputs and outputs usually share the same ground plane, sense is provided only for the +Output.
Figure 3. Measuring Output Ripple/Noise (PARD)
All external capacitors should have appropriate voltage ratings and be located as close to the converters as possible. Temperature variations for all relevant parameters should be taken into consideration. The most effective combination of external I/O capacitors will be a function of your line voltage and source impedance, as well as your particular load and layout conditions. Our Applications Engineers can recommend potential solutions and discuss the possibility of our modifying a given device's internal filtering to meet your specific requirements. Contact our Applications Engineering Group for additional details. Input Fusing Most applications and or safety agencies require the installation of fuses at the inputs of power conversion components. The LSN2 Series are not internally fused. Therefore, if input fusing is mandatory, either a normal-blow or a slow-blow fuse with a value no greater than twice the maximum input current calculated at low line with the converter's minimum efficiency should be
The remote sense line is part of the feedback control loop regulating the DC/DC converter's output. The sense line carries very little current and consequently requires a minimal cross-sectional-area conductor. As such, it is not a low-impedance point and must be treated with care in layout and cabling. Sense lines should be run adjacent to signals (preferably ground), and in cable and/or discrete-wiring applications, twisted-pair or similar techniques should be used. To prevent high frequency voltage differences between VOUT and Sense, we recommend installation of a 1000pF capacitor close to the converter. The sense function is capable of compensating for voltage drops between the +Output and +Sense pins that do not exceed 10% of VOUT. [VOUT(+) - Common] - [Sense(+) - Common] 10%VOUT Power derating (output current limiting) is based upon maximum output current and voltage at the converter's output pins. Use of trim and sense functions can cause the output voltage to increase, thereby increasing output power beyond the LSN2's specified rating. Therefore: (VOUT at pins) x (IOUT) rated output power
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LSN2 Series Page 5 of 14
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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
Output Overvoltage Protection LSN2 SIP Series DC/DC converters do not incorporate output overvoltage protection. In the extremely rare situation in which the device's feedback loop is broken, the output voltage may run to excessively high levels (VOUT = VIN). If it is absolutely imperative that you protect your load against any and all possible overvoltage situations, voltage limiting circuitry must be provided external to the power converter.
The internal 10.5 resistor between +Sense and +Output (see Figure 1) serves to protect the sense function by limiting the output current flowing through the sense line if the main output is disconnected. It also prevents output voltage runaway if the sense connection is disconnected. Note: If the sense function is not used for remote regulation, +Sense must be tied to +Output at the DC/DC converter pins. Remote On/Off Control The input-side remote On/Off Control is an external input signal available in either positive (no suffix) or negative ("N" suffix) polarity. Normally this input is controlled by the user's external transistor or relay. With simple external circuits, it may also be selected by logic outputs. Please note however that the actual control threshold levels vary somewhat with the PWM supply and therefore are best suited to "open collector" or "open drain" type logic. The On/Off control takes effect only when appropriate input power has been applied and stabilized (approximately 7msec). For positive polarity, the default operation leaves this pin open (unconnected) or HIGH. The output will then always be on (enabled) whenever appropriate input power is applied. Negative polarity models require the On/Off to be grounded to the -Input terminal or brought LOW to turn the converter on. To turn the converter off, for positive polarity models, ground the On/Off control or bring it LOW. For negative polarity, raise the On/Off at least to +2.5V to turn it off. Dynamic control of the On/Off must be capable of sinking or sourcing the
Figure 5. Inverting On/Off Control
Output Overcurrent Detection Overloading the power converter's output for an extended time will invariably cause internal component temperatures to exceed their maximum ratings and eventually lead to component failure. High-current-carrying components such as inductors, FET's and diodes are at the highest risk. LSN2 SIP Series DC/DC converters incorporate an output overcurrent detection and shutdown function that serves to protect both the power converter and its load. If the output current exceeds it maximum rating by typically 50% or if the output voltage drops to less than 98% of it original value, the LSN2's internal overcurrent-detection circuitry immediately turns off the converter, which then goes into a "hiccup" mode. While hiccupping, the converter will continuously attempt to restart itself, go into overcurrent, and then shut down. Once the output short is removed, the converter will automatically restart itself.
Figure 4. On/Off Control Using An External Open Collector Driver
Output Reverse Conduction Many DC/DC's using synchronous rectification suffer from Output Reverse Conduction. If those devices have a voltage applied across their output before a voltage is applied to their input (this typically occurs when another power supply starts before them in a power-sequenced application), they will either fail to start or self destruct. In both cases, the cause is the "freewheeling" or "catch" FET biasing itself on and effectively becoming a short circuit. LSN2 SIP DC/DC converters do not suffer from Output Reverse Conduction. They employ proprietary gate drive circuitry that makes them immune to moderate applied output overvoltages. Thermal Considerations and Thermal Protection The typical output-current thermal-derating curves shown below enable designers to determine how much current they can reliably derive from each model of the LSN2 SIPs under known ambient-temperature and air-flow conditions. Similarly, the curves indicate how much air flow is required to reliably deliver a specific output current at known temperatures.
control current (approximately 1mA max.) and not overdrive the input greater than the +VIN power input. Always wait for the input power to stabilize before activating the On/Off control. Be aware that a delay of several milliseconds occurs (see specifications) between activation of the control and the resulting change in the output. Power-up sequencing If a controlled start-up of one or more LSN2 Series DC/DC converters is required, or if several output voltages need to be powered-up in a given sequence, the On/Off control pin can be driven with an external open collector device as per Figure 4. Leaving the input of the on/off circuit closed during power-up will have the output of the DC/DC converter disabled. When the input to the external open collector is pulled high, the DC/DC converter's output will be enabled.
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LSN2 Series Page 6 of 14
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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
Solutions To improve start up, review the conditions above. One of the better solutions is to place a moderate size capacitor very close to the input terminals. You may need two parallel capacitors. A larger electrolytic or tantalum cap supplies the surge current and a smaller parallel low-ESR ceramic cap gives low AC impedance. Too large an electrolytic capacitor may have higher internal impedance (ESR) and/or lower the start up slew rate enough to upset the DC/DC's controller. Make sure the capacitors can tolerate reflected switching current pulses from the converter. The capacitors will not help if the input source has poor regulation. A converter which starts successfully at 3.3 Volts will turn off if the input voltage decays to below the input voltage theshold, regardless of external capacitance. Increase the input start up voltage if possible to raise the downward voltage spike. Also, make sure that the input voltage ramps up in a reasonably short time (less than a few milliseconds). If possible, move the input source closer to the converter to reduce ohmic losses in the input wiring. Remember that the input current is carried both by the wiring and the ground plane return. Make sure the ground plane uses adequate thickness copper. Run additional bus wire if necessary. Any added output capacitor should use just enough capacitance (and no more) to reduce output noise at the load and to avoid marginal threshold noise problems with external logic. An output cap will also "decouple" inductive reactance in the load. Certain kinds of electronic loads include "constant current" characteristics which destabilize the output with insufficient capacitance. If the wiring to the eventual load is long, consider placing this decoupling cap at the load. Use the Remote Sense input to avoid ohmic voltage drop errors. An elegant solution to start up problems is to apply the input voltage with the Remote On/Off control first in the off setting (for those converters with an On/ Off Control). After the specified start-up delay (usually under 20 mSec), turn on the converter. The controller will have already been stabilized. The short delay will not be noticed in most applications. Be aware of applications which need "power management" (phased start up). Finally, it is challenging to model some application circuits with absolute fidelity. How low is the resistance of your ground plane? What is the inductance (and distributed capacitance) of external wiring? Even a detailed mathematical model may not get all aspects of your circuit. Therefore it is difficult to give cap values which serve all applications. Some experimentation may be required. Pre-Biased Startup Newer systems with multiple power voltages have an additional problem besides startup sequencing. Some sections have power already partially applied (possibly because of earlier power sequencing) or have leakage power present so that the DC/DC converter must power up into an existing voltage. This power may either be stored in an external bypass capacitor or supplied by an active source. This "pre-biased" condition can also occur with some types of programmable logic or because of blocking diode leakage or small currents passed through forward biased ESD diodes. Conventional DC/DC's may fail to start up correctly if there is output voltage already present. And some external circuits are adversely affected when the low side MOSFET in a synchronous rectifier converter sinks current at start up.
The highest temperatures in LSN2 SIPs occur at their output inductor, whose heat is generated primarily by I 2 R losses. The derating curves were developed using thermocouples to monitor the inductor temperature and varying the load to keep that temperature below +110C under the assorted conditions of air flow and air temperature. Once the temperature exceeds +115C (approx.), the thermal protection will disable the converter. Automatic restart occurs after the temperature has dropped below +110C. As you may deduce from the derating curves and observe in the efficiency curves on the following pages, LSN2 SIPs maintain virtually constant efficiency from half to full load, and consequently deliver very impressive temperature performance even if operating at full load. Lastly, when LSN2 SIPs are installed in system boards, they are obviously subject to numerous factors and tolerances not taken into account here. If you are attempting to extract the most current out of these units under demanding temperature conditions, we advise you to monitor the output-inductor temperature to ensure it remains below +110C at all times. Start Up Considerations When power is first applied to the DC/DC converter, operation is different than when the converter is running and stabilized. There is some risk of start up difficulties if you do not observe several application features. Lower output voltage converters may have more problems here since they tend to have higher output currents. Operation is most critical with any combination of the following external factors: 1 - Low initial input line voltage and/or poor regulation of the input source. 2 - Full output load current on lower output voltage converters. 3 - Slow slew rate of input voltage. 4 - Longer distance to input voltage source and/or higher external input source impedance. 5 - Limited or insufficient ground plane. External wiring that is too small. 6 - Too small external input capacitance. Too high ESR. 7 - High output capacitance causing a start up charge overcurrent surge. 8 - Output loads with excessive inductive reactance or constant current characteristics. If the input voltage is already at the low limit before power is applied, the start up surge current may instantaneously reduce the voltage at the input terminals to below the specified minimum voltage. Even if this voltage depression is very brief, this may interfere with the on-board controller and possibly cause a failed start. Or the converter may start but the input current load will now drive the input voltage below its running low limit and the converter will shut down. If you measure the input voltage before start up with a Digital Voltmeter (DVM), the voltage may appear to be adequate. Limited external capacitance and/or too high a source impedance may cause a short downward spike at power up, causing an instantaneous voltage drop. Use an oscilloscope not a DVM to observe this spike. The converter's soft-start controller is sensitive to input voltage. What matters here is the actual voltage at the input terminals at all times. Symptoms of start-up difficulties may include failed started, output oscillation or brief start up then overcurrent shutdown. Since the input voltage is never absolutely constant, the converter may start up at some times and not at others.
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LSN2 Series Page 7 of 14
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LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters
D12 Models Resistor Trim Equation: 10500 RTRIM () = _____________ -1000 VO - 0.7525
VOUT RTRIM (k) 0.7525V Open 1.0V 41.424 1.2V 22.46 1.5V 13.05 1.8V 9.024 2.5V 5.009 3.3V 3.122 5V 1.472
The LSN2 series includes a pre-bias startup mode to prevent these initialization problems. Essentially, the converter acts as a simple buck converter until the output reaches its set point voltage at which time it converts to a synchronous rectifier design. This feature is variously called "monotonic" because the voltage does not decay (from low side MOSFET shorting) or produce a negative transient once the input power is applied and the startup sequence begins. Don't Use Pre-Biasing and Sequencing Together Normally, you would use startup sequencing on multiple DC/DC's to solve the Pre-Bias problem. By causing all power sources to ramp up together, no one source can dominate and force the others to fail to start. For most applications, do not use startup sequencing in a Pre-Bias application, especially with an external active power source. If you have active source pre-biasing, leave the Sequence input open so that the output will step up quickly and safely. A symptom of this condition is repeated failed starts. You can further verify this by removing the existing load and testing it with a separate passive resistive load which does not exceed full current. If the resistive load starts successfully, you may be trying to drive an external pre-biased active source. It may also be possible to use pre-bias and sequencing together if the PreBias source is in fact only a small external bypass capacitor slowly charged by leakage currents. Test your application to be sure. Output Adjustments The LSN2 series includes a special output voltage trimming feature which is fully compatible with competitive units. The output voltage may be varied using a single trim resistor from the Trim input to Power Common (pin 4) or an external DC trim voltage applied between the Trim input and Power Common. The output voltage range for W3 models is 0.75 to 3.3 Volts. For D12 models, the output range is 0.75 to 5 Volts. IMPORTANT: On W3 models only, for outputs greater than 3 Volts up to 3.3 Volts maximum, the input supply must be 4.5 Volts minimum. To retain proper regulation, do not exceed the 3.3V output. As with other trim adjustments, be sure to use a precision low-tempco resistor (100 ppm/C) mounted close to the converter with short leads. Also be aware that the output voltage accuracy is 2% (typical) therefore you may need to vary this resistance slightly to achieve your desired output setting. Two different trim equations are used for the W3 and D12 models. W3 Models Resistor Trim Equation: 21070 RTRIM () = _____________ -5110 VO - 0.7525 The W3 models fixed trim resistors to set the output voltage are:
VOUT (Typ.) RTRIM (k) 0.7525V Open 1.0V 80.021 1.2V 41.973 1.5V 23.077 1.8V 15.004 2.5V 6.947 3.3V 3.16
Voltage Trim The LSN2 Series may also be trimmed using an external voltage applied between the Trim input and Output Common. Be aware that the internal "load" impedance looking into trim pin is approximately 5k. Therefore, you may have to compensate for this in the source resistance of your external voltage reference. Use a low noise DC reference and short leads. Mount the leads close to the converter. Consider using a small bypass capacitor (0.1F ceramic) between trim and output common to avoid instability. Two different trim equations are used for the W3 and D12 models. W3 Models Voltage Trim Equation: VTRIM (in Volts) = 0.7 -(0.1698 x (VO - 0.7525)) The LSN2 W3 fixed trim voltages to set the output voltage are:
VOUT (Typ.) 0.7525V VTRIM Open 1.0V 0.6928V 1.2V 0.624V 1.5V 1.8V 2.5V 3.3V 0.267V
0.5731V 0.5221V 0.4033V
D12 Models Voltage Trim Equation: VTRIM (in Volts) = 0.7 -(0.0667 x (VO - 0.7525)) The LSN2 D12 fixed trim voltages to set the output voltage are:
VOUT VTRIM (V) 0.7525V Open 1.0V 0.6835 1.2V 0.670 1.5V 0.650 1.8V 0.630 2.5V 0.583 3.3V 0.530 5V 0.4166
Figure 6. Trim Connections
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Two Approaches There are two ways to manage these timing and voltage differences. Either the power up/down sequence can be controlled by discrete On/Off logic controls for each power supply (see Figure 7). Or the power up/down cycle is set by Sequencing or Tracking circuits. Some systems combine both methods. The first system (discrete On/Off controls) applies signals from an alreadypowered logic sequencer or dedicated microcontroller which turns on each downstream power section in cascaded series. This of course assumes all POL's have On/Off controls. A distinct advantage of the sequencing controller is that it can produce an "All On" output signal to state that the full system is stable and ready to go to work. For additional safety, the sequencer can monitor the output voltages of all downstream POL's with an A/D converter system. However the sequencer controller has some obvious difficulties besides extra cost, wiring and programming complexity. First, power is applied as a fast-rising, all-or-nothing step which may be unacceptable to certain circuits, especially large output bypass capacitors. These could force POL's into overcurrent shutdown. And some circuits (such as many linear regulators and some POL's) may not have convenient start-up controls. This requires designing and fabricating external power controls such as high-current MOSFET's. If the power up/down timing needs to be closely controlled, each POL must be characterized for start-up and down times. These often vary--one POL may stabilize in 15 milliseconds whereas another takes 50 milliseconds. Another problem is that the sequencing controller itself must be "already running" and stabilized before starting up other circuits. If there is a glitch in the system, the power up/down sequencer could get out of step with possible disastrous results. Lastly, changing the timing may require reprogramming the logic sequencer or rewriting software. Sequence/Track Input A different power sequencing solution is employed on DATEL's LSN2 DC/DC converter. After external input power is applied and the converter stabilizes, a high impedance Sequence/Track input pin accepts an external analog voltage. The output power voltage will then track this Sequence/Track input at a one-to-one ratio up to the nominal set point voltage for that converter. This Sequencing input may be ramped, delayed, stepped or otherwise phased as needed for the output power, all fully controlled by the user's simple external circuits. As a direct input to the converter's feedback loop, response to the Sequence/Track input is very fast (milliseconds). By properly controlling this Sequence pin, most operations of the discrete On/Off logic sequencer may be duplicated. The Sequence pin system does not use the converter's Enable On/Off control (unless it is a master emergency shut down system). Power Phasing Architectures Observe the simplified timing diagrams below. There are many possible power phasing architectures and these are just some examples to help you analyze your system. Each application will be different. Multiple output voltages may require more complex timing than that shown here.
LSN2 Power Sequencing Whereas in the old days, one master switch simultaneously turned on the power for all parts of a system, many modern systems require multiple supply voltages for different on-board sections. Typically the CPU or microcontroller needs 1.8 Volts or lower. Memory (particularly DDR) may use 1.8 to 2.5 Volts. Interface "glue" and "chipset" logic might use +3.3Vdc power while Input/ Output subsystems may need +5V. Finally, peripherals use 5V and/or 12V. Timing is Everything This mix of system voltages is being distributed by several local power solutions including Intermediate Bus Architecture (IBA) bus converters, Point-ofload (POL) DC/DC converters and sometimes a linear regulator, all sourced from a master AC power supply. While this mix of voltages is challenging enough, a further difficulty is the start-up and shutdown timing relationship between these power sources and relative voltage differences between them. For many systems, the CPU and memory must be powered up, boot-strap loaded and stabilized before the I/O section is turned on. This avoids uncommanded data bytes being transferred, compromising an active external network or placing the I/O section in an undefined mode. Or it keeps bad commands out of disk and peripheral controllers until they are ready to go to work. Another goal for staggered power-up is to avoid an oversize load applied to the master source all at once. A more serious reason to manage the timing and voltage differences is to avoid either a latchup condition in programmable logic (a latchup might ignore commands or would respond improperly to them) or a high current startup situation (which may damage on-board circuits). And on the power down phase, inappropriate timing or voltages can cause interface logic to send a wrong "epitaph" command.
Figure 7. Power Up/Down Sequencing Controller
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These diagrams illustrate the time and slew rate relationship between two typical power output voltages. Generally the Master will be a primary power voltage in the system which must be present first or coincident with any Slave power voltages. The Master output voltage is connected to the Slave's Sequence input, either by a voltage divider, divider-plus-capacitor or some other method. Several standard sequencing architectures are prevalent. They are concerned with three factors:

The time relationship between the Master and Slave voltages The voltage difference relationship between the Master and Slave The voltage slew rate (ramp slope) of each converter's output.
For most systems, the time relationship is the dominant factor. The voltage difference relationship is important for systems very concerned about possible latchup of programmable devices or overdriving ESD diodes. Lower slew rates avoid overcurrent shutdown during bypass cap charge-up. In Figure 18, two POL's ramp up at the same rate until they reach their different respective final set point voltages. During the ramp, their voltages are nearly identical. This avoids problems with large currents flowing between
Figure 10. Staggered or Sequential Phasing--Inclusive (Fixed Delays)
Figure 11. Staggered or Sequential Phasing--Exclusive (Fixed Cascaded Delays)
Figure 8. Coincident or Simultaneous Phasing (Identical Slew Rates)
Figures 10 and 11 show both delayed start up and delayed final voltages for two converters. Figure 10 is called "Inclusive" because the later starting POL finishes inside the earlier POL. The timing in Figure 10 is more easily built using a combined digital sequence controller and the Sequence/Track pin. Figure 11 is the same strategy as Figure 10 but with an "exclusive" timing relationship staggered approximately the same at power-up and power-down. Operation To use the Sequence pin after power start-up stabilizes, apply a rising external voltage to the Sequence input. As the voltage rises, the output voltage will track the Sequence input (gain = 1). The output voltage will stop rising when it reaches the normal set point for the converter. The Sequence input may optionally continue to rise without any effect on the output. Keep the Sequence input voltage below the converter's input supply voltage. Use a similar strategy on power down. The output voltage will stay constant until the Sequence input falls below the set point. Any strategy may be used to deliver the power up/down ramps. The circuits below show simple RC networks but you may also use operational amplifiers, D/A converters, etc.
logic systems which are not initialized yet. Since both end voltages are different, each converter reaches it's setpoint voltage at a different time.
Figure 9. Proportional or Ratiometric Phasing (Identical VOUT Time)
Circuits The circuits shown in Figures 12 through 14 introduce several concepts when using these Sequencing controls on Point-of-Load (POL) converters. These circuits are only for reference and are not intended as final designs ready for your application. Also, numerous connections are omitted for clarity.
LSN2 Series Page 10 of 14
Figure 9 shows two POL's with different slew rates in order to reach differing final voltages at about the same time.
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Figure 12. Wiring for Simultaneous Phasing Figure 14. Proportional Phasing
Figure 12 shows a basic Master (POL A) and Slave (POL B) connected so the POL B ramps up identically to POL A as shown in timing diagram, Figure 8. RC network R1 and C1 charge up at a rate set by the R1-C1 time constant, giving a roughly linear ramp. As POL A reaches 3.3VOUT (the setpoint of POL B), POL B will stop rising. POL A then continues rising until it reaches 5V. R1 should be significantly smaller than the internal bias current resistor from the Sequence pin. Start with a 20k value. We assume that the critical phase is only on power up therefore there is no provision for ramped power down. Figure 13 shows a single POL and the same RC network. However, we have added a FET at Q1 as an up/down control. When VIN power is applied to the POL, Q1 is biased on, shorting out the Sequence pin. When Q1's gate is biased off, R1 charges C1 and the POL's output ramps up at the R1-C1 slew rate. Note: Q1's gate would typically be controlled from some external digital logic.
Figure 15. Sequence/Track Simplified Equivalent Schematic
Guidelines for Sequence/Track Applications [1] Leave the converter's On/Off Enable control (if installed) in the On setting. Normally, you should just leave the On/Off pin open. [2] Allow the converter to stabilize (typically less than 20 mS after +VIN power on) before raising the Sequence input. Also, if you wish to have a ramped power down, leave +VIN powered all during the down ramp. Do not simply shut off power. [3] If you do not use the Sequence/Track pin, leave it open or tied to +VIN. If you wish to have a ramped power down (rather than a step down), add a small resistor in series with Q1's drain. Figure 14 shows both a RC ramp on Master POL A and a proportional tracking divider (R2 and R3) on POL B. We have also added an optional very small noise filter cap at C2. Figure 14's circuit corresponds roughly to Figure 9's timing for power up. [4] Observe the Output slew rate relative to the Sequence input. A rough guide is 2 Volts per millisecond maximum slew rate. If you exceed this slew rate on the Sequence pin, the converter will simply ramp up at it's maximum output slew rate (and will not necessarily track the faster Sequence input). The reason to carefully consider the slew rate limitation is in case you want two different POL's to precisely track each other.
Figure 13. Self-Ramping Power Up
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Power Good Output The Power Good Output consists of an unterminated BSS138 small signal field effect transistor and a dual window comparator input circuit driving the gate of the FET. Power Good is TRUE (open drain, high impedance state) if the converter's power output voltage is within about 10% of the setpoint. Thus, the PG TRUE condition indicates that the converter is approximately within regulation. Since an overcurrent condition occurs at about 2% output voltage reduction, the Power Good does not directly measure an output overcurrent condition at rated maximum output current. However, gross overcurrent or an output short circuit will set Power Good to FALSE (+0.2V saturation, low impedance condition). Using a simple connection to external logic (and returned to the converter's Common connection), the Power Good output is unterminated so that the user may adapt the output to a variety of logic families. The PG pin may therefore be used with logic voltages which are not necessarily the same as the input or output power voltages. Install an external pullup resistor to the logic supply voltage which is compatible with your logic system. When the Power Good is out of limit, the FET is at saturation, approximately +0.2V output. Keep this LOW (FALSE) pulldown current to less than 10mA. Please note that Power Good is briefly false during Sequence ramp-up. Ignore Power Good while in transition.
[5] Be aware of the input characteristics of the Sequence pin. The high input impedance affects the time constant of any small external ramp capacitor. And the bias current will slowly charge up any external caps over time if they are not grounded. The internal pull-up resistor to +VIN is typically 400k to 1M. Notice in the simplified Sequence/Track equivalent circuit (Figure 15) that a blocking diode effectively disconnects this circuit when the Sequence/ Track pin is pulled up to +VIN or left open. [6] Allow the converter to eventually achieve its full-rated setpoint output voltage. Do not remain in ramp up/down mode indefinitely. The converter is characterized and meets all its specifications only at the setpoint voltage (plus or minus any trim voltage). During the ramp-up phase, the converter is not considered fully in regulation. This may affect performance with excessive high current loads at turn-on. [7] The Sequence is a sensitive input into the feedback control loop of the converter. Avoid noise and long leads on this input. Keep all wiring very short. Use shielding if necessary. Consider adding a small parallel ceramic capacitor across the Sequence/Track input (see Figure 14) to block any external high frequency noise. [8] If one converter is slaving to another master converter, there will be a very short phase lag between the two converters. This can usually be ignored. [9] You may connect two or more Sequence inputs in parallel from two converters. Be aware of the increasing pull-up bias current and reduced input impedance. [10] Any external capacitance added to the converter's output may affect ramp up/down times and ramp tracking accuracy.
Figure 16. Equivalent Power Good Circuit
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MECHANICAL SPECIFICATIONS
Case B11
10/16 Amp Models
Pin 1 2 3 4 5 A I/O CONNECTIONS Function P68 Pin Function P68 +Output +Output +Sense In +Output Common Power Good Out * 6 7 8 B 9 10 Common +Input +Input VTRACK/Sequence Trim On/Off Control * Power Good output is optional. If not installed, the pin is omitted.
Case B12 6 Amp Models
Pin 1 2 3 A B 4 5 I/O CONNECTIONS Function P69 +Output VOUT Trim Common VTRACK/Sequence Power Good* +Input On/Off Control
* Power Good output is optional. If not installed, the pin is omitted.
DIMENSIONS ARE IN INCHES (MM)
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TYPICAL PERFORMANCE CURVES
C&D Technologies (NCL), Ltd. Milton Keynes, United Kingdom, Tel: 44 (0) 1908 615232 Internet: www.cd4power.com E-mail: ped.ltd@cdtechno.com C&D Technologies (DATEL) S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 Internet: www.cd4power.com E-mail: ped.sarl@cdtechno.com
C&D Technologies (DATEL), Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
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ISO 9001 REGISTERED
C&D Technologies (DATEL) GmbH Munchen, Germany Tel: 89-544334-0 Internet: www.cd4power.com E-mail: ped.gmbh@cdtechno.com C&D Technologies KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-6354-2025 Int.: www.cd4power.jp Email: sales_tokyo@cdtechno.com, sales_osaka@cdtechno.com
01/06
Email: sales@cdtechno.com
DS-0558
China Shanghai, People's Republic of China Tel: 86-50273678 Internet: www.cd4power.com E-mail: shanghai@cdtechno.com
C&D Technologies (DATEL), Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered trademark of C&D Technologies, Inc..
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